Salary
Not Disclosed
Location
Hyderabad
Highlights
World-class verification team, cutting-edge technology, RISC-V expertise, collaborative environment.
Description
Job Summary
pJoin the forefront of innovation with SiFive, the pioneer behind RISC-V. As an Engineer I in our Hardware Engineering team, you will be part of a world-class group verifying complex CPU pipelines and memory subsystems. Your role is pivotal in ensuring the architectural and microarchitectural correctness of the Memory Management Unit (MMU).Responsibilities
- Participate in block-level and subsystem-level verification of MMU, including TLBs, page table walkers, and memory protection mechanisms.
- Write, execute, and debug directed and random test cases to verify complex architectural scenarios.
- Analyze functional and code coverage metrics to identify verification gaps and write cover groups/assertions.
- Collaborate with design and architecture teams to understand microarchitectural specifications and root-cause design bugs.
Required Skills
- Verilog
- C/C++
- Python
- Pipeline Verification
- Memory Management Unit (MMU)
Required Skills Explained
- Strong foundation in computer and CPU core architecture, including pipelines, caches, virtual memory, and paging mechanisms.
- Good programming knowledge of Verilog for Hardware Description Languages/High-Level Verification Languages (HDL/HVL).
- Basic experience with scripting languages such as Python, Perl, or Bash for automation and debugging tasks.
Who is this for
pThis role is ideal for recent graduates or early-career engineers with a strong foundation in computer and CPU core architecture. Experience with RISC-V ISA, privileged architecture specifications, and assembly-level programming is a plus.Why This Job is a Good Opportunity
ulliJoin a pioneering company that is revolutionizing the future of compute by introducing RISC-V technology to high-performance applications.liWork on complex CPU pipelines and memory subsystems, contributing to cutting-edge advancements in hardware engineering.liCollaborate with a world-class team of innovative engineers who are passionate about driving technological change.Interview Preparation Tips
- Revise core concepts of computer architecture, including CPUs, memory systems, and virtual memory mechanisms.
- Practice writing and debugging test cases for CPU verification scenarios using Verilog and scripting languages.
- Prepare to discuss real-world applications of RISC-V ISA (Instruction Set Architecture) in hardware design and verification.
Career Growth in This Role
pThe role of an Engineer I offers significant growth opportunities, particularly in advancing your expertise in CPU verification and RISC-V architecture. With experience, you can transition into more complex projects or take on leadership roles within the team. The collaborative environment at SiFive also provides ample opportunities to learn from industry experts and contribute to groundbreaking innovations.pAs you progress, you may have the chance to mentor junior engineers, further refine your skills in advanced CPU design verification, and explore new areas of RISC-V technology. This position is ideal for those seeking a challenging career that drives real-world impact through cutting-edge engineering solutions.Explore More Opportunities
Skills
Frequently Asked Questions
What is the role of MMU verification?You will verify the Memory Management Unit (MMU) including TLBs, page table walkers, and memory protection mechanisms to ensure architectural correctness.
What programming languages are required for this position?Good knowledge in Verilog, C/C++, Python is necessary. Basic scripting experience with languages like Perl or Bash is also preferred.
Is prior experience required for this role?While not mandatory, prior internship or relevant coursework in CPU or ASIC design verification would be beneficial.